1. Field of the Invention
The present invention relates to the test techniques and testability architectures used in testing integrated circuits. More specifically, the invention pertains to test techniques applied to testing of user-configurable arrays before they are configured by the user.
2. The Prior Art
User-configurable gate arrays consist of logic circuits or blocks that can be connected together by configurable interconnections, such as anti-fuse elements, to implement a desired circuit function. The configurable interconnect consists of interconnect layers such as metallization, and configurable devices which, when programmed, establish electrical connections between the interconnect layers. However, before configuring the circuit to implement a particular function, all the individual modules in the array and all the input/output (I/O) modules and buffers are isolated from one another. This presents a challenging test problem.
Before the circuit is configured by the user, all of the active circuits in such integrated circuits such as logic modules, I/O modules, configuring circuits, etc., must be tested and guaranteed to be fully functional and meet all required specifications. In addition, all passive interconnect circuits such as metallization interconnect, anti-fuse elements, feed-thru pass transistors, must also be free of defects and guaranteed. This is necessary so that a customer configuring such a circuit can expect a fully functional, high quality integrated circuit after his application circuit is mapped into the device. It is thus imperative that test architectures and test techniques be developed to solve this problem, namely, how to guarantee full functionality and spec of a one-time programmable user-configurable array circuit before circuit before the circuit is configured by the user.
User configurable arrays or PLDs (programmable logic devices) which use erasable elements to implement their interconnect do not have to contend with this problem since the array can be configured to implement any circuit pattern, be fully tested and later erased to the "blank" state for reconfiguration.